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FAN4803
8-Pin PFC and PWM Controller Combo
Features
* Internally synchronized PFC and PWM in one 8-pin IC * Patented one-pin voltage error amplifier with advanced input current shaping technique * Peak or average current, continuous boost, leading edge PFC (Input Current Shaping Technology) * High efficiency trailing-edge current mode PWM * Low supply currents; start-up: 150A typ., operating: 2mA typ. * Synchronized leading and trailing edge modulation * Reduces ripple current in the storage capacitor between the PFC and PWM sections * Overvoltage, UVLO, and brownout protection * PFC VCCOVP with PFC Soft Start
General Description
The FAN4803 is a space-saving controller for power factor corrected, switched mode power supplies that offers very low start-up and operating currents. Power Factor Correction (PFC) offers the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply fully compliant to IEC1000-3-2 specifications. The FAN4803 includes circuits for the implementation of a leading edge, average current "boost" type PFC and a trailing edge, PWM. The FAN4803-1's PFC and PWM operate at the same frequency, 67kHz. The PFC frequency of the FAN4803-2 is automatically set at half that of the 134kHz PWM. This higher frequency allows the user to design with smaller PWM components while maintaining the optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting for enhanced system reliability.
Block Diagram
7 VEAO 4 35A
-1
7V
+ -
PFC OFF
VCC
17.5V 16.2V + -
REF VCC OVP
COMP
VREF GND 2
COMP
M3 M4 PFC CONTROL LOGIC PFC OUT 1
M1
M2 R1 M7 C1 30pF
LEADING EDGE PFC ONE PIN ERROR AMPLIFIER 3 ISENSE
-4
+ +
PFC ILIMIT
VCC
-
COMP
SOFT START
TRAILING EDGE PWM
-1V
-
PFC/PWM UVLO OSCILLATOR PFC - 67kHz PWM - 134kHz
-
VREF VDC 26k
DUTY CYCLE LIMIT
5
PWM COMPARATOR PWM CONTROL LOGIC
40k 1.2V 6 ILIMIT
COMP
+ -
COMP
PWM OUT 8
+
M6 1.5V
- +
DC ILIMIT
REV. 1.2.2 5/20/02
FAN4803
PRODUCT SPECIFICATION
Pin Configuration
FAN4803 8-Pin PDIP (P08) 8-Pin SOIC (S08)
PFC OUT GND ISENSE VEAO 1 2 3 4 TOP VIEW 8 7 6 5 PWM OUT VCC ILIMIT VDC
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME PFC OUT GND ISENSE VEAO VDC ILIMIT VCC PWM OUT PFC driver output Ground Current sense input to the PFC current limit comparator PFC one-pin error amplifier input PWM voltage feedback input PWM current limit comparator input Positive supply (may require an external shunt regulator) PWM driver output FUNCTION
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter ICC Current (average) VCC MAX ISENSE Voltage Voltage on Any Other Pin Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC Min Max 40 18.3 1 VCC + 0.3 1 1 1.5 150 150 260 110 160 Unit mA V V V A A J C C C C/W C/W
-5 GND - 0.3
-65
Operating Conditions
Temperature Range FAN4803CS-X FAN4803CP-X 0C to 70C 0C to 70C
2
REV. 1.2.2 5/20/02
PRODUCT SPECIFICATION
FAN4803
Electrical Characteristics
Unless otherwise specified, VCC = 15V, TA = Operating Temperature Range (Note 1) Symbol Parameter One-pin Error Amplifier VEAO Output Current VEAO Output Current Line Regulation VCC OVP Comparator Threshold Voltage PFC ILIMIT Comparator Threshold Voltage Delay to Output DC ILIMIT Comparator Threshold Voltage Delay to Output Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Dead Time PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Impedance Output Low Voltage Output High Impedance Output High Voltage Rise/Fall Time PWM Duty Cycle Range Output Low Impedance Output Low Voltage Output High Impedance Output High Voltage Rise/Fall Time Supply VCC Clamp Voltage (VCCZ) ICC = 10mA Start-up Current VCC = 11V, CL = 0 Operating Current VCC = 15V, CL = 0 Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis 16.7 17.5 0.2 2.5 12 2.9 18.3 0.4 4 12.5 3.4 V mA mA V V FAN4803-2 FAN4803-1 IOUT = -100mA IOUT = -10mA, VCC = 8V IOUT = 100mA, VCC = 15V CL = 1000pF 13.5 0-41 0-49.5 0-47 8 0.8 0.7 8 14.2 50 0-50 0-50 15 1.5 1.5 15 % % V V V ns VEAO > 7.0V,ISENSE = -0.2V VEAO < 4.0V,ISENSE = 0V IOUT = -100mA IOUT = -10mA, VCC = 8V IOUT = 100mA, VCC = 15V CL = 1000pF 13.5 0 90 95 8 0.8 0.7 8 14.2 50 15 1.5 1.5 15 % % V V V ns TA = 25C 10V < VCC < 15V Over Line and Temp PFC Only 60 67 1 2 67 0.45 74 kHz % % kHz s Conditions TA = 25C, VEAO = 6V FAN4803-1 TA = 25C, VEAO = 6V 10V < VCC < 15V, VEAO = 6V Min 31.5 34.0 TYP 34.0 36.5 0.1 15.5 -0.9 16.3 -1 150 1.5 150 MAX UNITS 36.5 39.0 0.3 16.8 -1.15 300 1.6 300 A A A V V ns V ns
1.4
60 0.3
74.5 0.65
11.5 2.4
Note: 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. REV. 1.2.2 5/20/02
3
FAN4803
PRODUCT SPECIFICATION
Functional Description
The FAN4803 consists of an average current mode boost Power Factor Corrector (PFC) front end followed by a synchronized Pulse Width Modulation (PWM) controller. It is distinguished from earlier combo controllers by its low pin count, innovative input current shaping technique, and very low start-up and operating currents. The PWM section is dedicated to peak current mode operation. It uses conventional trailing-edge modulation, while the PFC uses leadingedge modulation. This patented Leading Edge/Trailing Edge (LETE) modulation technique helps to minimize ripple current in the PFC DC buss capacitor. The FAN4803 is offered in two versions. The FAN4803-1 operates both PFC and PWM sections at 67kHz, while the FAN4803-2 operates the PWM section at twice the frequency (134kHz) of the PFC. This allows the use of smaller PWM magnetics and output filter components, while minimizing switching losses in the PFC stage. In addition to power factor correction, several protection features have been built into the FAN4803. These include soft start, redundant PFC over-voltage protection, peak current limiting, duty cycle limit, and under voltage lockout (UVLO). See Figure 12 for a typical application.
control of the PWM stage. The current ramp is offset internally by 1.2V and then compared against the opto feedback voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power drivers capable of directly driving the gate of a power MOSFET with peak currents up to 1A. Both outputs are actively held low when VCC is below the UVLO threshold level.
VCC
VCC is the power input connection to the IC. The VCC startup current is 150A . The no-load ICC current is 2mA. VCC quiescent current will include both the IC biasing currents and the PFC and PWM output currents. Given the operating frequency and the MOSFET gate charge (Qg), average PFC and PWM output currents can be calculated as IOUT = Qg x F. The average magnetizing current required for any gate drive transformers must also be included. The VCC pin is also assumed to be proportional to the PFC output voltage. Internally it is tied to the VCCOVP comparator (16.2V) providing redundant high-speed over-voltage protection (OVP) of the PFC stage. VCC also ties internally to the UVLO circuitry, enabling the IC at 12V and disabling it at 9.1V. VCC must be bypassed with a high quality ceramic bypass capacitor placed as close as possible to the IC. Good bypassing is critical to the proper operation of the FAN4803. VCC is typically produced by an additional winding off the boost inductor or PFC Choke, providing a voltage that is proportional to the PFC output voltage. Since the VCCOVP max voltage is 16.2V, an internal shunt limits VCC overvoltage to an acceptable value. An external clamp, such as shown in Figure 1, is desirable but not necessary.
VCC
Detailed Pin Descriptions
VEAO
This pin provides the feedback path which forces the PFC output to regulate at the programmed value. It connects to programming resistors tied to the PFC output voltage and is shunted by the feedback compensation network.
ISENSE
This pin ties to a resistor or current sense transformer which senses the PFC input current. This signal should be negative with respect to the IC ground. It internally feeds the pulseby-pulse current limit comparator and the current sense feedback signal. The ILIMIT trip level is -1V. The ISENSE feedback is internally multiplied by a gain of four and compared against the internal programmed ramp to set the PFC duty cycle. The intersection of the boost inductor current downslope with the internal programming ramp determines the boost off-time.
1N4148
1N4148
1N5246B
VDC
This pin is typically tied to the feedback opto-collector. It is tied to the internal 5V reference through a 26k resistor and to GND through a 40k resistor.
GND
Figure 1. Optional VCC Clamp
ILIMIT
This pin is tied to the primary side PWM current sense resistor or transformer. It provides the internal pulse-by-pulse current limit for the PWM stage (which occurs at 1.5V) and the peak current mode feedback path for the current mode 4
VCC is internally clamped to 16.7V minimum, 18.3V maximum. This limits the maximum VCC that can be applied to the IC while allowing a VCC which is high enough to trip the VCCOVP. The max current through this zener is 10mA. External series resistance is required in order to limit the current through this Zener in the case where the VCC voltage exceeds the zener clamp level.
REV. 1.2.2 5/20/02
PRODUCT SPECIFICATION
FAN4803
GND
GND is the return point for all circuits associated with this part. Note: a high-quality, low impedance ground is critical to the proper operation of the IC. High frequency grounding techniques should be used.
Power Factor Correction
Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage. This is defined as a unity power factor is (one). A common class of nonlinear load is the input of a most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. Peak-charging effect, which occurs on the input filter capacitor in such a supply, causes brief highamplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the FAN4803 uses a boostmode DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current that the converter draws from the power line matches the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACRMS. The other condition is that the current that the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. Since the boost converter topology in the FAN4803 PFC is of the current-averaging type, no slope compensation is required.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn ON right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 2 shows a typical trailing edge control scheme.
L1 + DC I1 VIN
SW2
I2
I3 I4
SW1 C1
RL
RAMP
VEAO REF U3 + EA - DFF RAMP OSC U4 CLK + - U1 R Q D U2 Q CLK VSW1 TIME
TIME
Figure 2. Typical Trailing Edge Control Scheme.
REV. 1.2.2 5/20/02
5
FAN4803
PRODUCT SPECIFICATION
In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 3 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns OFF and Switch 2 (SW2) turns ON at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method, substantially reducing dissipation in the high-voltage PFC capacitor.
Programming Resistor Value
Equation 1 calculates the required programming resistor value.
Rp = VBOOST - VEAO 400V - 50V . = = 113M . IPGM 35A
(1)
PFC Voltage Loop Compensation
The voltage-loop bandwidth must be set to less than 120Hz to limit the amount of line current harmonic distortion. A typical crossover frequency is 30Hz. Equation 1, for simplicity, assumes that the pole capacitor dominates the error amplifier gain at the loop unity-gain frequency. Equation 2 places a pole at the crossover frequency, providing 45 degrees of phase margin. Equation 3 places a zero one decade prior to the pole. Bode plots showing the overall gain and phase are shown in Figures 5 and 6. Figure 4 displays a simplified model of the voltage loop.
CCOMP =
CCOMP =
Typical Applications
One Pin Error Amp
The FAN4803 utilizes a one pin voltage error amplifier in the PFC section (VEAO). The error amplifier is in reality a current sink which forces 35A through the output programming resistor. The nominal voltage at the VEAO pin is 5V. The VEAO voltage range is 4 to 6V. For a 11.3M resistor chain to the boost output voltage and 5V steady state at the VEAO, the boost output voltage would be 400V.
Pin R p x V BOOST x VEAO x COUT x (2 x x f)
300W
2
(2)
11.3M x 400V x 0.5V x 220F x (2 x x 30Hz)2
CCOMP = 16nF
L1 + DC I1 VIN
SW2
I2
I3 I4
SW1 C1
RL
RAMP
VEAO U3 + EA -
REF
VEAO + - CMP U1
DFF R Q D U2 Q CLK VSW1
TIME
RAMP OSC U4 CLK
TIME
Figure 3. Typical Leading Edge Control Scheme.
6
REV. 1.2.2 5/20/02
PRODUCT SPECIFICATION
FAN4803
Internal Voltage Ramp
1 2 x x f x CCOMP 1 = 330k 62 8 x 30Hz x 16nF .
1 f x RCOMP 2xx 10
(3)
RCOMP = RCOMP =
CZERO =
The internal ramp current source is programmed by way of the VEAO pin voltage. Figure 7 displays the internal ramp current vs. the VEAO voltage. This current source is used to develop the internal ramp by charging the internal 30pF +12/ -10% capacitor. See Figures 10 and 11. The frequency of the internal programming ramp is set internally to 67kHz.
PFC Current Sense Filtering
(4)
CZERO =
1 = 016 F . 6.28 x 3Hz x 330k
In DCM, the input current wave shaping technique used by the FAN4803 could cause the input current to run away. In order for this technique to be able to operate properly under DCM, the programming ramp must meet the boost inductor current down-slope at zero amps. Assuming the programming ramp is zero under light load, the OFF-time will be terminated once the inductor current reaches zero.
VO
60 Power Stage Overall Gain Compensation Network Gain
11.3M FAN4803 IOUT 220F RLOAD 667 VEAO 330k 15nF - 0.15F POWER STAGE COMPENSATION FAN4803
40
20 IVEAO 34A GAIN (dB)
VEAO +
0
-20
-40
Figure 4. Voltage Control Loop
-60 0.1
1
10 FREQUENCY (Hz)
100
1000
Figure 5. Voltage Loop Gain
0
50 Power Stage Overall Compensation Network FF @ -55C 40 TYP @ -55C TYP @ ROOM TEMP IRAMP (A) 30 TYP @ 155C SS @ 155C 20
50
PHASE ()
100
150
10
200 0.1
0 1 10 FREQUENCY (Hz) 100 1000 0 1 2 3 4 5 6 7 VEAO (V)
Figure 6. Voltage Loop Phase
Figure 7. Internal Ramp Current vs. VEAO
REV. 1.2.2 5/20/02
7
FAN4803
PRODUCT SPECIFICATION
Subsequently the PFC gate drive is initiated, eliminating the necessary dead time needed for the DCM mode. This forces the output to run away until the VCC OVP shuts down the PFC. This situation is corrected by adding an offset voltage to the current sense signal, which forces the duty cycle to zero at light loads. This offset prevents the PFC from operating in the DCM and forces pulse-skipping from CCM to noduty, avoiding DMC operation. External filtering to the current sense signal helps to smooth out the sense signal, expanding the operating range slightly into the DCM range, but this should be done carefully, as this filtering also reduces the bandwidth of the signal feeding the pulse-bypulse current limit signal. Figure 9 displays a typical circuit for adding offset to ISENSE at light loads.
sequence. Once disabled, the VEAO pin charges HIGH by way of the external components until the PFC duty cycle goes to zero, disabling the PFC. The VCC OVP resets once the VCC discharges below 16.2V, enabling the VEAO current sink and discharging the VEAO compensation components until the steady state operating point is reached. It should be noted that, as shown in Figure 8, once the VEAO pin exceeds 6.5V, the internal ramp is defeated. Because of this, an external Zener can be installed to reduce the maximum voltage to which the VEAO pin may rise in a shutdown condition. Clamping the VEAO pin externally to 7.4V will reduce the time required for the VEAO pin to recover to its steady state value.
UVLO PFC Start-Up and Soft Start
During steady state operation VEAO draws 35A. At start-up the internal current mirror which sinks this current is defeated until VCC reaches 12V. This forces the PFC error voltage to VCC at the time that the IC is enabled. With leading edge modulation VCC on the VEAO pin forces zero duty on the PFC output. When selecting external compensation components and VCC supply circuits VEAO must not be prevented from reaching 6V prior to VCC reaching 12V in the turn-on sequence. This will guarantee that the PFC stage will enter soft-start. Once VCC reaches 12V the 35A VEAO current sink is enabled. VEAO compensation components are then discharged by way of the 35A current sink until the steady state operating point is reached. See Figure 8. Once VCC reaches 12V both the PFC and PWM are enabled. The UVLO threshold is 9.1V providing 2.9V of hysteresis.
Generating VCC
An internal clamp limits overvoltage to VCC. This clamp circuit ensures that the VCC OVP circuitry of the FAN4803 will function properly over tolerance and temperature while protecting the part from voltage transients. This circuit allows the FAN4803 to deliver 15V nominal gate drive at PWM OUT and PFC OUT, sufficient to drive low-cost IGBTs. It is important to limit the current through the Zener to avoid overheating or destroying it. This can be done with a single resistor in series with the VCC pin, returned to a bias supply of typically 14V to 18V. The resistor value must be chosen to meet the operating current requirement of the FAN4803 itself (4.0mA max) plus the current required by the two gate driver outputs.
PFC Soft Recovery Following VCC OVP
The FAN4803 assumes that VCC is generated from a source that is proportional to the PFC output voltage. Once that source reaches 16.2V the internal current sink tied to the VEAO pin is disabled just as in the soft start turn-on
VCC 0 VEAO 0 VOUT 0
10V/div.
C23 0.01F R29 20k R28 20k R4 1k
to BR1 -Ve
10V/div.
PFC GATE
CR16 1N4148
C16 1F
R19 10k ISENSE C5 0.0082F
10V/div.
R3 0.15 3W
VBOOST 0 200ms/Div.
200V/div.
VCC RTN
(see Figure 12)
Figure 8. PFC Soft Start
Figure 9. ISENSE Offset for Light Load Conditions
8
REV. 1.2.2 5/20/02
PRODUCT SPECIFICATION
FAN4803
VCC OVP
VCC is assumed to be a voltage proportional to the PFC output voltage, typically a bootstrap winding off the boost inductor. The VCC OVP comparator senses when this voltage exceeds 16V, and terminates the PFC output drive while disabling the VEAO current sink. Once the VEAO current sink is disabled, the VEAO voltage will charge unabated, except for a diode clamp to VCC, reducing the PFC pulse width. Once the VCC rail has decreased to below 16.2V the VEAO sink will be enabled, discharging external VEAO compensation components until the steady state voltage is reached. Given that 15V on VCC corresponds to 400V on the PFC output, 16V on VCC corresponds to an OVP level of 426V.
Component Reduction
Components associated with the VRMS and IRMS pins of a typical PFC controller such as the ML4824 have been eliminated. The PFC power limit and bandwidth does vary with line voltage. Double the power can be delivered from a 220 V AC line versus a 110 V AC line. Since this is a combination PFC/PWM, the power to the load is limited by the PWM stage.
VISENSE
VC1 RAMP
GATE DRIVE OUTPUT
Figure 10. Typical Peak Current Mode Waveforms
VOUT = 400V RP VEAO 4 C1 30pF RCOMP CZERO CCOMP 35A R1 5V
VC1
+ -
COMP
GATE OUTPUT
3
ISENSE
-4
VI SENSE
Figure 11. FAN4803 PFC Control
REV. 1.2.2 5/20/02
9
FAN4803
PRODUCT SPECIFICATION
LINE F1 5A 250V J1-1 R24 470k 0.5W
C19 4.7nF 250VAC C4 0.47F 250VAC GBU4J BR1 600V 4A L3
TH1 10 5A
102T L2 1000H FQP9N50 Q5 R1 36 FQP9N50 Q2 R2 36 1N5246B CR5 16V 0.5W
RURP860 CR1 8A, 600V
NEUTRAL J1-2 C20 4.7nF 250VAC
C1 220F 450V
C16 0.01F
R22 10k
R3 0.15 3W 1N5818 CR7 R30 200 T2 1 10 3 4 C29 0.01F R38 22
FQP9N50 Q4 R8 36 UF4005 CR3
P6KE51CA CR18 51V
Q1 2N3906
R23 10k
C18 4.7nF
R36 220
C25 0.01F 500V 12V
T1 MBR3060PT CR2 30A 60V CR2 30A, 60V C2 2200F L1 25H 1N4148 CR8 C11 1000F L2 C9 1F R31 10 C21 1F C3 1F R14 150 2W
J2-1
R13 5.8M
C7 0.1F R7 10
R27 20k 3W
12VRET R26 20k 3W J2-2 C26 0.01F 500V
C23 0.01F
R29 20k
CR16 IN4148
R19 10k
C22 1F
4T 1N4148 CR15 FQP9N50 Q3 R6 1.2k C14 4.7F
R12 5.8M
R28 20k 1 2
FAN4803
PFC GND PWM VCC
8 7 6 5
1N5818 CR10
R5 36
5
R9 1.5k U3
1
R4 1k 1N5818 CR12 R25 390k 7.0V C8 0.15F C15 0.015F C5 8.2nF
3 4
R11 150 R32 100 C10 2.2nF R10 0.75 3W CR4 UF4005
2 4
R37 330
ISENSE ILIMIT VEAO VDC
C17 0.1F
R15 9.09k
C13 1nF
C6 1F
C28 1F
R21 10k C27 0.01F CR11 1N5818 CR9 1N52468
R20 510 U2
R17 3.3k
3 1
C12 0.1F
R18 1k R16 2.37k
2 RC431A
Figure 12. Typical Application Circuit. Universal Input 240W 12V DC Output
10
REV. 1.2.2 5/20/02
PRODUCT SPECIFICATION
FAN4803
Mechanical Dimensions
Package: S08 8 Pin SOIC
0.189 - 0.199 (4.80 - 5.06) 8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACE ) S 0.050 BS C (1.27 BS C) 0.059 - 0.069 (1.49 - 1.75) 0-8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51) S ATING PLANE E
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
Package: P08 8-Pin PDIP
0.365 - 0.385 (9.27 - 9.77) 0.055 - 0.065 (1.39 - 1.65) 8
PIN 1 ID
0.240 - 0.260 0.299 - 0.335 (6.09 - 6.60) (7.59 - 8.50)
0.020 MIN (0.51 MIN) (4 PLACES)
1 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.020 (0.40 - 0.51) SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
REV. 1.2.2 5/20/02
11
FAN4803
PRODUCT SPECIFICATION
Ordering Information
Part Number FAN4803CS-1 FAN4803CS-2 FAN4803CP-1 FAN4803CP-2 PFC/PWM Frequency 67kHz / 67kHz 67kHz / 134kHz 67kHz / 67kHz 67kHz / 134kHz Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C Package 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin PDIP (P08) 8-Pin PDIP (P08)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/02 0.0m 003 Stock#DS30004803 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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